Iguanas and Electronics

Card Pans - Block Diagrams

This is the "planned" architectural design for my card-based computer. The Control logic will not be a card slotted into the backplane, but pretty much everything else will be. I need to learn more about the various sound chips to lay out a sound card, but I imagine it will be complicated. I have dropped the Address Bus from the design as too limiting, but have not reallocated those 16-lanes yet... perhaps an I/O bus?I am not including any real details about flags or control here, to keep things simple... this is basically just an overview with block diagrams laid out to kind of look like the cards.
The general purpose register card is already designed and manufactured, with three of them assembled and working. These are very basic devices, and might end up being entirely replaced by counters or shift-registers for efficiency purposes (if any register can be incremented or shifted, we save having to copy values from the general purpose register to the special register, perform the operation, and copy back). The general purpose register will also act as an interface for I/O operations... buffering front-panel input and holding "output" values for 7-segment displays.
I expect there to be at least four general purpose registers.
The counter card can read and write the data bus via transceivers, as the ICs used are not 3-state. This allows the ALU to write directly to the counter, after a jump or branch calculation. The counter always outputs to a pair of headers and supports increment, decrement, and reset signals. I think this design needs to generate an out-of-bounds signal, when the counter rolls from 0000 to FFFF or from FFFF to 0000.

I expect there will be several counters, optimally two for RAM, two for ROM, and one for the Stack. If we include a separate "Return Address Stack", that will require a counter to drive the address as well.
I am prototyping an alternate counter card that includes a dedicated adder and  "offset-register" to make relative jumps easy and efficient. This would require some extra controls to change the offset register, but could save a lot of clock cycles when compared to using the ALU to calculate relative jumps. This design would need e out-of-bounds signal generation based on overflow or underflow from the adder logic to detect when the address rolls over (the address being somewhat independent of the actual counter value).
I expect there will be several counters, optimally two for RAM, two for ROM, and one for the Stack. If we use two stacks, that would require a sixth counter for the second stack. Not all counters would need to support offsets, but in those cases the outputs from the 74LS193a can be jumpered directly to the address output headers.
The shift register card is very similar to the counter card, with the exception being that bits are shifted left or right instead of values being incremented or decremented.
 I expect there to be only one shift register needed.
The RAM card can rad from or output to the data bus via transceivers. While the RAM is 3-state, it is CMOS based and the transceivers will provide needed buffering of the bus. Addressing has been moved from the backplane to a pair of headers, controlled by transceivers or "one of two 4-bit word selectors", allowing for efficient addressing changes.
I expect there to be at least one RAM card, but will need an additional one for the Stack, and possibly a third for a "Return Stack"... if the stack is divided for efficiency purposes. 
The ROM card is functionally identical to the RAM card, as the EEPROMs and SRAM ICs used have identical pinouts and control signal requirements. While technically writable, the plan is to have a firmware card that does not receive WE signals from the control logic. 
The current plan is to have two ROM cards, one as firmware (to contain useful functions that can be called from user programs in RAM), and one that can act as storage (with the WE signal enabled to store programs).
The ALU can write to the data bus via a buffer register (the 74LS181 is not 3-state). It receives inputs via sets of headers for the "A" input and the "B" input. The design was to have "A" and "B" simply be registers, but I plan to experiment with making them selectable, so that one input could toggle between a register and a counter (like the PC), while the other could toggle between a pair of registers. This would allow for more efficient calculations and comparisons without needing to spend cycles moving values between registers).
There will be a single ALU in the computer, but it may be cost-effective to design the ALU in halves for PCB manufacture (minimum orders are five PCBs).
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