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Writing, Iguanas, and Electronics

This page will describe the instruction set in general terms, providing links to the detailed information for each. Subject to change, this will be the first draft version.

Phase I Device List:

The first phase will be the minimal hardware setup, with a reduced array of registers and counters. This phase will be very short, as the stack is critically important to the operation of the CPU.

    1 - Program Counter
    3 - RAM
    5 - X Counter
    A - A Register
    B - B Register
    F - Output Cache Register

 

Phase II Device List:

The second phase may be a long one, as it includes all of the important registers and counters needed for operation of the CPU. This phase will end when ROM and peripherals are added.

    1 - Program Counter
    2 - Stack Pointer
    3 - RAM
    4 - Stack
    5 - X Counter
    6 - Y Counter
    7 - Z Counter
    A - A Register
    B - B Register
    C - C Register
    F - Output Cache Register

 

Phase III Device List:

The third phase introduces additional functionality like long-term storage (ROM), and peripherals like audio and video systems. Peripherals are planned to interface via two 16-bit registers, but this may change in the future.

    1 - Program Counter
    2 - Stack Pointer
    3 - RAM
    4 - Stack
    5 - X Counter
    6 - Y Counter
    7 - Z Counter

    8 - ROM Pointer
    9 - ROM
    A - A Register
    B - B Register
    C - C Register
    D - Peripheral Register 1
    E - Peripheral Register 2
    F - Output Cache Register