For me to understand the fetch, decode, execute cycle... well, I need to work through it, I guess. So, here is my first crack at the clock timings for the four possible MOV operations. 

 

 

The above are planned assembly code instructions for moving data between registers, loading values into a register, and moving values between registers and memory. The ALU will output to registers and memory as well, but I will leave that until much later.

 

 

The "Register to Register MOV" operation is pretty simple. The instruction is fetched and decoded, and the PC is incremented during the first step. The second step is the execute phase, where one register outputs and on the rising clock, the other register writes. I have provisions for delayed and inverted clocks in my design, but I am hoping they will not be needed to prevent timing issues.

 

 

 

The "Value to Register MOV" instruction is basically the same as the Register to Register version. Because the PC was already incremented, the correct address is loaded and we need only output from memory and write to the selected register. The PC needs to be incremented a second time, to ensure the next fetch operation is on an instruction and not the value we just copied to a register.

 

 

 

A "Memory Location to Register MOV" is a little more involved, as the address needs to be loaded into a separate pointer and made active. Like the Value to Register MOV, the PC needs to be incremented once to make sure it points to the next instruction. On the third step, the memory (as addressed by the temporary address register) outputs, and the selected register writes. The PC needs to be made active once the memory operation is completed.

 

 

 

The "Register to Memory MOV" instruction is nearly identical to the "Memory to Register MOV", with only the final output and write targets switched.